Each substream has a 1-to-1 association with a DMA channel.
The link array is first because it needs to be aligned on a 32-byte boundary, so putting it first will ensure alignment without padding the structure.
]: array of link descriptors : which DMA controller (0, 1, ...) : which DMA channel on the controller (0, 1, 2, ...) : pointer to the DMA channel's registers : IRQ for this DMA channel : pointer to the substream object, needed by the ISR : bus address of the STX or SRX register to use : physical address of the LD buffer : index into link of the link currently being processed : physical address of the DMA buffer : physical address of the next period to process : physical address of the byte after the end of the DMA period_size: the size of a single period : the number of periods in the DMA buffer
|struct ccsr_dma_channel __iomem *||dma_channel|
|struct fsl_dma_link_descriptor||link [NUM_DMA_LINKS]|
|struct snd_pcm_substream *||substream|